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| 19-1418; Rev 0; 12/98 MAX3875 Evaluation Kit General Description The MAX3875 evaluation kit (EV kit) simplifies evaluation of the MAX3875, a 2.5Gbps clock-recovery and data-retiming IC. The EV kit enables testing of all MAX3875 functions. SMA connectors are provided for the differential PECL-compatible data and clock outputs, as well as system loopback functions. The differential data and clock outputs have 50 attenuators on-board to allow direct connection to a highspeed oscilloscope. The MAX3875 EV kit comes configured for +3.3V operation and consumes approximately 220mA. ____________________________Features o SMA Connections for All System I/Os o Test Point for Monitoring Loss-of-Lock (LOL) o Single +3.3V Power-Supply Operation o Fully Assembled and Tested Evaluates: MAX3875 _______________Ordering Information PART MAX3875EVKIT TEMP. RANGE -40C to +85C IC PACKAGE 5mm 32 TQFP __________________________________________________________________Component List DESIGNATION C1, C2, C3, C5-C10, C13, C14, C15, C21-C26, C29, C30 C11 C12 C19 C20 U1 L1, L2, L3 R1 R7, R11, R15, R19 R8, R12, R16, R20 QTY DESCRIPTION DESIGNATION R9, R13, R17, R21 20 0.1F, 25V min ceramic capacitors R10, R14, R18, R22 R25, R28 1 1 1 1 1 3 1 4 4 Open 1F, 10V min X7R ceramic capacitor 33F, 20%, 10V min tantalum capacitor 2.2F, 25V min ceramic capacitor MAX3875EHJ (5mm 32-pin TQFP) 56nH inductors Coilcraft* 0805HS-560TKBC 392, 1% resistor 24, 5% resistors 27, 5% resistors None None 1 1 MAX3875 evaluation kit MAX3875 data sheet R26 LOL, GND, +3.3V JP2 JP10 JP2, JP10 SDI+, SDI-, SLBI+, SLBI-, SCLKO+, SCLKO-, SDO+, SDOD1 QTY 4 4 1 1 3 1 1 2 DESCRIPTION 130, 1% resistors 220, 5% resistors 10k, 5% resistors 10k variable resistor Test points 2-pin header (0.1" centers) 3-pin header (0.1" centers) Shunts 8 Edge-mount SMA connectors 1 Red LED * Coilcraft: phone 847-639-6400, fax 847-639-1469 ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX3875 Evaluation Kit Evaluates: MAX3875 _______________Detailed Description The MAX3875 EV kit is fully assembled and factory tested. It enables testing of all MAX3875 functions. tions can be monitored at the high-impedance LOL test point. A TTL high (LED off) indicates PLL frequency lock while a TTL low (LED on) indicates a loss-of-lock condition. Note that the LOL circuitry will not detect a loss-ofpower condition (refer to the MAX3875 data sheet). Test Equipment Required * * * * +3.3V power supply with 300mA current capability Signal-source, 2.5Gbps minimum capability Jitter analyzer capable of 2.5Gbps performance Oscilloscope with at least 3GHz performance Layout Considerations The MAX3875's performance can be greatly affected by circuit board layout and design. Use good high-frequency design techniques, including minimizing ground inductances and using fixed-impedance transmission lines on the data and clock signals. Connections The serial data inputs (SDI+, SDI-) have on-board ACcoupling capacitors. All of the MAX3875 data and clock outputs (SDO+, SDO-, SCLKO+, SCLKO-) are terminated on-board with 50, PECL, 2X attenuators. Configured in this way, these outputs can be directly connected to the 50 inputs of a high-speed oscilloscope for analysis. VCC - 2V DC SDO+ RF & DC 50 BIAS-T RF Setup 1) Select either the serial data inputs, pins 2 and 3 of JP10 (SDI EN), or the system loopback inputs, pins 1 and 2 of JP10 (SLBI EN), with jumper JP10. 2) Verify that the shunt across jumper JP2 is in place. 3) Connect the +3.3V power supply to the appropriate terminals marked on the EV kit and apply power. 4) Connect a 2.5Gbps PRBS NRZ signal to the selected inputs with 50 cables. 5) Connect the outputs to a 50 high-speed oscilloscope. Jitter analysis and product performance can also be observed by appropriately interfacing the EV kit with a bit-error-rate tester (BERT) and a jitter analyzer. MAX3875 EVKIT SDOOUTPUT ATTENUATORS REMOVED ON SDO+ AND SCLKO+ SCLKO+ 50 BER TESTER VCC - 2V DC RF & DC 50 BIAS-T RF CLOCK IN DATA IN ERROR DETECTOR SCLKO50 Interfacing with ECL Test Equipment Not all jitter analyzers and bit-error-rate testers can easily interface with the EV kit's PECL output signal levels. If your test equipment requires standard ECL levels, then bias tees are required (Figure 1). For example, if using an HP BERT, you must : 1) Remove the data and clock output attenuators for those signal lines you intend to observe. For example, if you intend to observe SDO+, then open R9 and R10, and short R7 and R8. 2) Use a 50 bias tee to bias the MAX3875's outputs. One adjustment is available on the MAX3875 EV kit. PHADJ R26, although not required, can be used to shift the sampling edge of the recovered clock relative to the center of the data eye. (Be sure to remove jumper JP2 if you intend to adjust PHADJ.) PLL frequency lock condi- Figure 1. ECL Interface to Test Equipment Table 1. Jumpers and Test Points NAME JP2 TYPE 2-Pin DESCRIPTION Disables the Phase Adjustment (R26) Used to select between the serial data input (labeled SDI EN) and the system loopback function (labeled SLBI EN) of the MAX3875. Used to monitor LOL voltage level NORMAL POSITION Shorted (disabled) JP10 3-Pin -- LOL Test Point -- 2 _______________________________________________________________________________________ MAX3875 Evaluation Kit Evaluates: MAX3875 L1 56nH VCCPLL C21 0.1F C22 0.1F C29 0.1F VCCVCO C23 0.1F C24 0.1F VCCOUT C25 0.1F C26 0.1F C3 0.1F C14 0.1F C30 0.1F C15 0.1F L2 +3.3V C19 33F 10V GND 56nH 1 2 C20 2.2F 56nH L3 +3.3V PHASE ADJ DISABLE 3 PHASE ADJ R26 10k 1 2 JP2 D1 C13 0.1F C11 OPEN R28 10k LOL R9 130 +3.3V VCC SDO+ SDO24 23 22 21 20 19 18 17 R17 130 +3.3V VCCOUT C9 0.1F R19 24 R20 27 R22 220 R13 130 +3.3V VCCOUT VCCOUT R15 24 R18 220 R16 27 C8 0.1F R11 24 R12 27 R14 220 VCCOUT C7 0.1F R7 24 R10 220 R8 27 R1 392 SDO+ R25 10k +3.3V VCCPLL C12 1F 32 GND 31 FIL+ 30 FIL- 29 GND 28 PHADJ+ 27 PHADJ- 26 GND 25 LOL 1 C1 0.1F VCCPLL 2 3 4 5 SDIC2 0.1F VCCPLL VCCPLL 1 SLBI EN 2 3 JP10 SDI EN 6 7 8 GND GND VCC SDI+ SDIVCC SIS GND SLBI+ SLBIGND GND GND VCC VCC VCC SDO- SDI+ U1 MAX3875 VCC VCC SCLKO+ SCLKOVCC SCLKO+ SCLKO- 9 10 11 12 13 14 15 16 GND R21 130 +3.3V VCCPLL SLBI+ C5 0.1F C10 0.1F VCCVCO VCCPLL SLBI- C6 0.1F Figure 2. MAX3875 EV Kit Schematic _______________________________________________________________________________________ 3 MAX3875 Evaluation Kit Evaluates: MAX3875 1.0" Figure 3. MAX3875 EV Kit Component Placement Guide 1.0" Figure 4. MAX3875 EV Kit PC Board Layout--Component Side 1.0" Figure 5. MAX3875 EV Kit PC Board Layout--Solder Side 4 _______________________________________________________________________________________ MAX3875 Evaluation Kit Evaluates: MAX3875 1.0" Figure 6. MAX3875 EV Kit PC Board Layout--Ground Plane 1.0" Figure 7. MAX3875 EV Kit PC Board Layout--Power Plane _______________________________________________________________________________________ 5 MAX3875 Evaluation Kit Evaluates: MAX3875 NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. |
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